The present invention relates to semiconductor memory devices, and more particularly, to a system for providing burst mode transfers for use with memory devices.
Semiconductor devices, such as memory devices, are commonly used as information storage devices in digital systems. As the amount of information that needs to be stored increases, it has become increasingly important to have an efficient way of accessing such memory devices.
Generally, memory read or write operations are initiated in response to external signals provided to the memory by a controller, such as a processor. In most cases, the amount of information that needs to be transferred during a memory access is large. In addition, the rate at which the information is propagated from a processor to a memory device and vice versa continues to increase. Therefore, increasing performance demands are being placed on the ability to read and write information to memory devices.
Information is transferred between a processor and a memory device via a data bus. However, a bus has limited bandwidth, and so, efficient bus utilization is generally highly desirable. For example, one way to read data from sequential address locations of a memory device is to transmit a sequence of read requests that include respective addresses of the data to be read. However, using this technique means that a substantial portion of the bus bandwidth is used as overhead to provide the address information. One way to reduce the required overhead is to use memory devices that include burst mode technology.
Burst mode technology is one way to efficiently utilize the bus and to increase bus bandwidth. A burst mode device can realize high performance due to its high data transfer capability. For example, a processor coupled to a burst mode memory device can read data from a number of sequential storage addresses by requesting a read operation that includes a starting address and a count parameter indicating the number of sequential addresses to read. The read request results in a continuous flow of data from the specified sequential addresses of the memory device without the requirement of requesting data from each address individually. This is referred to as synchronous operation and is available for both read and write operations. Thus, using the burst mode, it is possible to reduce instruction overhead and increase bus efficiency for synchronous operations.
However, burst mode technology memory devices are still required to perform normal random access operations (i.e., asynchronous operation), where accessing data associated with only one address or several random address locations is required. As a result, a typical burst mode device includes an additional interface pin (mode pin) or requires a special instruction (mode command) to differentiate between synchronous and asynchronous operations. However, this is undesirable since increasing the number of interface pins increases the size, cost and complexity of the device, and requiring additional mode commands increases overhead and decreases bus efficiency.
Therefore, it would be desirable to have a way to perform synchronous and asynchronous memory operations without having to add additional interface pins or special commands to differentiate between the modes of operation.
The present invention includes a system for differentiating between synchronous and asynchronous modes of operation associated with a memory device and generating burst mode control signals accordingly. The system determines a mode of operation from signals associated with accessing the device. Furthermore, the operating mode determination is independent of the clock signal timing, so that clock timing restrictions found in conventional circuits are avoided. This eliminates the need for additional interface pins or special mode commands.
In one embodiment of the present invention, apparatus is provided to set a burst mode in a memory device. The apparatus includes a first signal buffer that receives an address control signal and produces a buffered address control signal. A mode detection circuit is included that receives the buffered address control signal and produces a burst control signal. The apparatus also includes a core access trigger circuit that receives the burst control signal and generates a core access signal that is used to begin a core access for burst mode operation of the memory.
In another embodiment of the present invention, a method is provided for setting a burst mode in a memory device. The method includes the steps of receiving an address control signal to produce a buffered address control signal, producing a burst control signal from the buffered address control signal, and generating a core access signal from the burst control signal, the core access signal is used to begin a core access for burst mode operation of the memory.